f trackpad: drop wheel, check error, drop invert x y, add rotate 90

This commit is contained in:
crides 2023-02-05 02:22:19 -06:00
parent 1e6185439a
commit 52b43a72e8
3 changed files with 83 additions and 60 deletions

View file

@ -110,7 +110,7 @@ static int pinnacle_sample_fetch(const struct device *dev, enum sensor_channel c
#ifdef CONFIG_PINNACLE_TRIGGER
static void set_int(const struct device *dev, const bool en) {
const struct pinnacle_config *config = dev->config;
int ret = gpio_pin_interrupt_configure_dt(&config->dr, en ? GPIO_INT_LEVEL_ACTIVE : GPIO_INT_DISABLE);
int ret = gpio_pin_interrupt_configure_dt(&config->dr, en ? GPIO_INT_EDGE_TO_ACTIVE : GPIO_INT_DISABLE);
if (ret < 0) {
LOG_ERR("can't set interrupt");
}
@ -156,7 +156,6 @@ static void pinnacle_work_cb(struct k_work *work) {
static void pinnacle_gpio_cb(const struct device *port, struct gpio_callback *cb, uint32_t pins) {
struct pinnacle_data *data = CONTAINER_OF(cb, struct pinnacle_data, gpio_cb);
const struct device *dev = data->dev;
#if defined(CONFIG_PINNACLE_TRIGGER_OWN_THREAD)
k_sem_give(&data->gpio_sem);
#elif defined(CONFIG_PINNACLE_TRIGGER_GLOBAL_THREAD)
@ -169,30 +168,58 @@ static int pinnacle_init(const struct device *dev) {
struct pinnacle_data *data = dev->data;
const struct pinnacle_config *config = dev->config;
pinnacle_write(dev, PINNACLE_STATUS1, 0); // Clear CC
pinnacle_write(dev, PINNACLE_Z_IDLE, 0); // No Z-Idle packets
if (config->sleep_en) {
pinnacle_write(dev, PINNACLE_SYS_CFG, PINNACLE_SYS_CFG_EN_SLEEP);
LOG_WRN("pinnacle start");
int ret;
ret = pinnacle_write(dev, PINNACLE_STATUS1, PINNACLE_SYS_CFG_RESET);
if (ret < 0) {
LOG_ERR("can't reset %d", ret);
return ret;
}
k_msleep(20);
ret = pinnacle_write(dev, PINNACLE_STATUS1, 0); // Clear CC
if (ret < 0) {
LOG_ERR("can't write %d", ret);
return ret;
}
k_usleep(50);
ret = pinnacle_write(dev, PINNACLE_Z_IDLE, 0); // No Z-Idle packets
if (ret < 0) {
LOG_ERR("can't write %d", ret);
return ret;
}
if (config->sleep_en) {
ret = pinnacle_write(dev, PINNACLE_SYS_CFG, PINNACLE_SYS_CFG_EN_SLEEP);
if (ret < 0) {
LOG_ERR("can't write %d", ret);
return ret;
}
}
uint8_t feed_cfg2 = PINNACLE_FEED_CFG2_EN_IM;
if (config->no_taps) {
pinnacle_write(dev, PINNACLE_FEED_CFG2, PINNACLE_FEED_CFG2_DIS_TAP);
feed_cfg2 |= PINNACLE_FEED_CFG2_DIS_TAP;
}
if (config->rotate_90) {
feed_cfg2 |= PINNACLE_FEED_CFG2_ROTATE_90;
}
ret = pinnacle_write(dev, PINNACLE_FEED_CFG2, feed_cfg2);
if (ret < 0) {
LOG_ERR("can't write %d", ret);
return ret;
}
uint8_t feed_cfg1 = PINNACLE_FEED_CFG1_EN_FEED;
if (config->invert_x) {
feed_cfg1 |= PINNACLE_FEED_CFG1_INV_X;
}
if (config->invert_y) {
feed_cfg1 |= PINNACLE_FEED_CFG1_INV_Y;
}
if (feed_cfg1) {
pinnacle_write(dev, PINNACLE_FEED_CFG1, feed_cfg1);
ret = pinnacle_write(dev, PINNACLE_FEED_CFG1, feed_cfg1);
}
if (ret < 0) {
LOG_ERR("can't write %d", ret);
return ret;
}
#ifdef CONFIG_PINNACLE_TRIGGER
data->dev = dev;
gpio_pin_configure_dt(&config->dr, GPIO_INPUT);
gpio_init_callback(&data->gpio_cb, pinnacle_gpio_cb, BIT(config->dr.pin));
int ret = gpio_add_callback(config->dr.port, &data->gpio_cb);
ret = gpio_add_callback(config->dr.port, &data->gpio_cb);
if (ret < 0) {
LOG_ERR("Failed to set DR callback: %d", ret);
return -EIO;
@ -225,12 +252,11 @@ static const struct sensor_driver_api pinnacle_driver_api = {
static struct pinnacle_data pinnacle_data_##n; \
static const struct pinnacle_config pinnacle_config_##n = { \
.bus = COND_CODE_1(DT_INST_ON_BUS(0, i2c), (I2C_DT_SPEC_INST_GET(0)), (SPI_DT_SPEC_INST_GET(0, SPI_OP_MODE_MASTER | SPI_WORD_SET(8) | SPI_LINES_SINGLE | SPI_TRANSFER_MSB, 0))), \
.invert_x = DT_INST_PROP(0, invert_x), \
.invert_y = DT_INST_PROP(0, invert_y), \
.rotate_90 = DT_INST_PROP(0, rotate_90), \
.sleep_en = DT_INST_PROP(0, sleep), \
.no_taps = DT_INST_PROP(0, no_taps), \
COND_CODE_1(CONFIG_PINNACLE_TRIGGER, (.dr = GPIO_DT_SPEC_GET(DT_DRV_INST(0), dr_gpios),), ) \
}; \
DEVICE_DT_INST_DEFINE(n, pinnacle_init, device_pm_control_nop, &pinnacle_data_##n, &pinnacle_config_##n, POST_KERNEL, CONFIG_SENSOR_INIT_PRIORITY, &pinnacle_driver_api);
DEVICE_DT_INST_DEFINE(n, pinnacle_init, NULL, &pinnacle_data_##n, &pinnacle_config_##n, POST_KERNEL, CONFIG_SENSOR_INIT_PRIORITY, &pinnacle_driver_api);
DT_INST_FOREACH_STATUS_OKAY(CIRQUE_INST)

View file

@ -11,49 +11,48 @@
#define PINNACLE_DUMMY 0xFB
// Registers
#define PINNACLE_FW_ID 0x00 // ASIC ID.
#define PINNACLE_FW_VER 0x01 // Firmware Version Firmware revision number.
#define PINNACLE_STATUS1 0x02 // Contains status flags about the state of Pinnacle.
#define PINNACLE_SYS_CFG 0x03 // Contains system operation and configuration bits.
#define PINNACLE_SYS_CFG_EN_SLEEP BIT(2)
#define PINNACLE_SYS_CFG_SHUTDOWN BIT(1)
#define PINNACLE_SYS_CFG_RESET BIT(0)
#define PINNACLE_FW_ID 0x00 // ASIC ID.
#define PINNACLE_FW_VER 0x01 // Firmware Version Firmware revision number.
#define PINNACLE_STATUS1 0x02 // Contains status flags about the state of Pinnacle.
#define PINNACLE_SYS_CFG 0x03 // Contains system operation and configuration bits.
#define PINNACLE_SYS_CFG_EN_SLEEP BIT(2)
#define PINNACLE_SYS_CFG_SHUTDOWN BIT(1)
#define PINNACLE_SYS_CFG_RESET BIT(0)
#define PINNACLE_FEED_CFG1 0x04 // Contains feed operation and configuration bits.
#define PINNACLE_FEED_CFG1_EN_FEED BIT(0)
#define PINNACLE_FEED_CFG1_ABS_MODE BIT(1)
#define PINNACLE_FEED_CFG1_DIS_FILT BIT(2)
#define PINNACLE_FEED_CFG1_DIS_X BIT(3)
#define PINNACLE_FEED_CFG1_DIS_Y BIT(4)
#define PINNACLE_FEED_CFG1_INV_X BIT(6)
#define PINNACLE_FEED_CFG1_INV_Y BIT(7)
#define PINNACLE_FEED_CFG2 0x05 // Contains feed operation and configuration bits.
#define PINNACLE_FEED_CFG2_EN_IM BIT(0) // Intellimouse
#define PINNACLE_FEED_CFG2_DIS_TAP BIT(1) // Disable all taps
#define PINNACLE_FEED_CFG2_DIS_SEC BIT(2) // Disable secondary tap
#define PINNACLE_FEED_CFG2_DIS_SCRL BIT(3) // Disable scroll
#define PINNACLE_FEED_CFG2_DIS_GE BIT(4) // Disable GlideExtend
#define PINNACLE_FEED_CFG2_SWAP_XY BIT(7) // Swap X & Y
#define PINNACLE_CAL_CFG 0x07 // Contains calibration configuration bits.
#define PINNACLE_PS2_AUX 0x08 // Contains Data register for PS/2 Aux Control.
#define PINNACLE_SAMPLE 0x09 // Sample Rate Number of samples generated per second.
#define PINNACLE_Z_IDLE 0x0A // Number of Z=0 packets sent when Z goes from >0 to 0.
#define PINNACLE_Z_SCALER 0x0B // Contains the pen Z_On threshold.
#define PINNACLE_SLEEP_INTERVAL 0x0C // Sleep Interval
#define PINNACLE_SLEEP_TIMER 0x0D // Sleep Timer
#define PINNACLE_AG_PACKET0 0x10 // trackpad Data (Pinnacle AG)
#define PINNACLE_2_2_PACKET0 0x12 // trackpad Data
#define PINNACLE_REG_COUNT 0x18
#define PINNACLE_FEED_CFG1 0x04 // Contains feed operation and configuration bits.
#define PINNACLE_FEED_CFG1_EN_FEED BIT(0)
#define PINNACLE_FEED_CFG1_ABS_MODE BIT(1)
#define PINNACLE_FEED_CFG1_DIS_FILT BIT(2)
#define PINNACLE_FEED_CFG1_DIS_X BIT(3)
#define PINNACLE_FEED_CFG1_DIS_Y BIT(4)
#define PINNACLE_FEED_CFG1_INV_X BIT(6)
#define PINNACLE_FEED_CFG1_INV_Y BIT(7)
#define PINNACLE_FEED_CFG2 0x05 // Contains feed operation and configuration bits.
#define PINNACLE_FEED_CFG2_EN_IM BIT(0) // Intellimouse
#define PINNACLE_FEED_CFG2_DIS_TAP BIT(1) // Disable all taps
#define PINNACLE_FEED_CFG2_DIS_SEC BIT(2) // Disable secondary tap
#define PINNACLE_FEED_CFG2_DIS_SCRL BIT(3) // Disable scroll
#define PINNACLE_FEED_CFG2_DIS_GE BIT(4) // Disable GlideExtend
#define PINNACLE_FEED_CFG2_ROTATE_90 BIT(7) // Swap X & Y
#define PINNACLE_CAL_CFG 0x07 // Contains calibration configuration bits.
#define PINNACLE_PS2_AUX 0x08 // Contains Data register for PS/2 Aux Control.
#define PINNACLE_SAMPLE 0x09 // Sample Rate Number of samples generated per second.
#define PINNACLE_Z_IDLE 0x0A // Number of Z=0 packets sent when Z goes from >0 to 0.
#define PINNACLE_Z_SCALER 0x0B // Contains the pen Z_On threshold.
#define PINNACLE_SLEEP_INTERVAL 0x0C // Sleep Interval
#define PINNACLE_SLEEP_TIMER 0x0D // Sleep Timer
#define PINNACLE_AG_PACKET0 0x10 // trackpad Data (Pinnacle AG)
#define PINNACLE_2_2_PACKET0 0x12 // trackpad Data
#define PINNACLE_REG_COUNT 0x18
#define PINNACLE_PACKET0_BTN_PRIM BIT(0) // Primary button
#define PINNACLE_PACKET0_BTN_SEC BIT(1) // Secondary button
#define PINNACLE_PACKET0_BTN_AUX BIT(2) // Auxiliary (middle?) button
#define PINNACLE_PACKET0_X_SIGN BIT(4) // X delta sign
#define PINNACLE_PACKET0_Y_SIGN BIT(5) // Y delta sign
#define PINNACLE_PACKET0_BTN_PRIM BIT(0) // Primary button
#define PINNACLE_PACKET0_BTN_SEC BIT(1) // Secondary button
#define PINNACLE_PACKET0_BTN_AUX BIT(2) // Auxiliary (middle?) button
#define PINNACLE_PACKET0_X_SIGN BIT(4) // X delta sign
#define PINNACLE_PACKET0_Y_SIGN BIT(5) // Y delta sign
struct pinnacle_data {
int16_t dx, dy;
int8_t wheel;
uint8_t btn;
#ifdef CONFIG_PINNACLE_TRIGGER
const struct device *dev;
@ -76,7 +75,7 @@ struct pinnacle_config {
#elif DT_INST_ON_BUS(0, spi)
const struct spi_dt_spec bus;
#endif
bool invert_x, invert_y, sleep_en, no_taps;
bool rotate_90, sleep_en, no_taps;
#ifdef CONFIG_PINNACLE_TRIGGER
const struct gpio_dt_spec dr;
#endif

View file

@ -2,9 +2,7 @@ properties:
dr-gpios:
type: phandle-array
description: Data ready pin for the trackpad
invert-x:
type: boolean
invert-y:
rotate-90:
type: boolean
sleep:
type: boolean