implement gpio_165 driver
This is an input-only gpio driver for use with 74x165 style parallel-input shift registers, (using SPI peripheral) The user can choose to either use cs-gpios of spi or load-gpios for connecting to the SH/LD pin of the shift register. The difference is that cs-gpios will keep the input latch enabled while idle, and load-gpios will instead pulse the SH/LD signal before the register content is shifted. In both cases the gpio should be configured GPIO_ACTIVE_HIGH.
This commit is contained in:
Purdea Andrei
parent
ace11e327f
commit
2403ecb046
5 changed files with 296 additions and 0 deletions
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@ -4,5 +4,6 @@
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zephyr_library_named(zmk__drivers__gpio)
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zephyr_library_include_directories(${CMAKE_SOURCE_DIR}/include)
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zephyr_library_sources_ifdef(CONFIG_GPIO_165 gpio_165.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_595 gpio_595.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_MAX7318 gpio_max7318.c)
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@ -3,3 +3,4 @@ menuconfig ZMK_DRIVERS_GPIO
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rsource "Kconfig.max7318"
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rsource "Kconfig.595"
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rsource "Kconfig.165"
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25
app/drivers/gpio/Kconfig.165
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25
app/drivers/gpio/Kconfig.165
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@ -0,0 +1,25 @@
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# 165 GPIO configuration options
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# Copyright (c) 2022 The ZMK Contributors
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# SPDX-License-Identifier: MIT
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DT_COMPAT_ZMK_GPIO_165 := zmk,gpio-165
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menuconfig GPIO_165
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bool "165 Parallel Input Shift Register SPI driver"
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default $(dt_compat_enabled,$(DT_COMPAT_ZMK_GPIO_165))
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depends on SPI
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select HAS_DTS_GPIO
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select ZMK_DRIVERS_GPIO
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help
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Enable driver for 165 shift register chip using SPI.
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if GPIO_165
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config GPIO_165_INIT_PRIORITY
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int "Init priority"
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default 75
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help
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Device driver initialization priority.
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endif #GPIO_165
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235
app/drivers/gpio/gpio_165.c
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235
app/drivers/gpio/gpio_165.c
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@ -0,0 +1,235 @@
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/*
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* Copyright (c) 2022 The ZMK Contributors
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*
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* SPDX-License-Identifier: MIT
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*/
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#define DT_DRV_COMPAT zmk_gpio_165
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/**
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* @file Driver for 165 parallel-input shift register, SPI-based GPIO driver.
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*/
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#include <errno.h>
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#include <zephyr/kernel.h>
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#include <zephyr/device.h>
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#include <zephyr/init.h>
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#include <zephyr/sys/byteorder.h>
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#include <zephyr/drivers/gpio.h>
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#include <zephyr/drivers/spi.h>
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#define LOG_LEVEL CONFIG_GPIO_LOG_LEVEL
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#define LOAD_GPIOS_LEN(n) DT_INST_PROP_LEN(n, load_gpios)
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#define LOAD_GPIO_CFG_INIT(idx, inst_idx) \
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GPIO_DT_SPEC_GET_BY_IDX(DT_DRV_INST(inst_idx), load_gpios, idx)
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(gpio_165);
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/** Configuration data */
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struct reg_165_config {
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/* gpio_driver_data needs to be first */
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struct gpio_driver_config common;
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struct spi_dt_spec bus;
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uint8_t ngpios;
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const struct gpio_dt_spec *load_gpios;
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size_t load_gpios_len;
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};
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/** Runtime driver data */
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struct reg_165_drv_data {
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/* gpio_driver_data needs to be first */
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struct gpio_driver_config data;
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struct k_sem lock;
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};
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static int reg_165_read_registers(const struct device *dev, uint32_t *value) {
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const struct reg_165_config *config = dev->config;
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int ret = 0;
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uint8_t nread = config->ngpios / 8;
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uint32_t reg_data = 0;
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/* Allow a sequence of 1-4 registers in sequence, lowest byte is for the first in the chain */
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const struct spi_buf rx_buf[1] = {{
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.buf = ((uint8_t *)®_data) + (4 - nread),
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.len = nread,
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}};
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const struct spi_buf_set rx = {
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.buffers = rx_buf,
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.count = ARRAY_SIZE(rx_buf),
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};
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for (int i = 0; i < config->load_gpios_len; i++) {
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int err = gpio_pin_set_dt(&config->load_gpios[i], 0);
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if (err) {
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LOG_ERR("Unable to set pin %u on %s to idle value '0'", config->load_gpios[i].pin,
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config->load_gpios[i].port->name);
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return err;
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}
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}
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for (int i = 0; i < config->load_gpios_len; i++) {
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int err = gpio_pin_set_dt(&config->load_gpios[i], 1);
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if (err) {
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LOG_ERR("Unable to set pin %u on %s to idle value '1'", config->load_gpios[i].pin,
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config->load_gpios[i].port->name);
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return err;
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}
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}
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ret = spi_read_dt(&config->bus, &rx);
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*value = sys_be32_to_cpu(reg_data);
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if (ret < 0) {
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LOG_ERR("spi_read FAIL %d\n", ret);
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return ret;
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}
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return 0;
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}
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/**
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* @brief Setup the pin direction (input or output)
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*
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* @param dev Device struct of the 165
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* @param pin The pin number
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* @param flags Flags of pin or port
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*
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* @return 0 if successful, failed otherwise
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*/
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static int setup_pin_dir(const struct device *dev, uint32_t pin, int flags) {
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if ((flags & GPIO_INPUT) == 0U) {
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return -ENOTSUP;
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}
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return 0;
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}
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static int reg_165_pin_config(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags) {
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int ret;
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/* Can't do SPI bus operations from an ISR */
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if (k_is_in_isr()) {
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return -EWOULDBLOCK;
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}
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if ((flags & GPIO_OPEN_DRAIN) != 0U) {
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return -ENOTSUP;
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};
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ret = setup_pin_dir(dev, pin, flags);
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if (ret) {
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LOG_ERR("165: error setting pin direction (%d)", ret);
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}
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return ret;
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}
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static int reg_165_port_get_raw(const struct device *dev, uint32_t *value) {
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struct reg_165_drv_data *const drv_data = (struct reg_165_drv_data *const)dev->data;
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int ret;
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/* Can't do SPI bus operations from an ISR */
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if (k_is_in_isr()) {
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return -EWOULDBLOCK;
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}
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k_sem_take(&drv_data->lock, K_FOREVER);
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ret = reg_165_read_registers(dev, value);
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k_sem_give(&drv_data->lock);
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return ret;
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}
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static int reg_165_port_set_masked_raw(const struct device *dev, uint32_t mask, uint32_t value) {
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return -ENOTSUP;
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}
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static int reg_165_port_set_bits_raw(const struct device *dev, uint32_t mask) { return -ENOTSUP; }
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static int reg_165_port_clear_bits_raw(const struct device *dev, uint32_t mask) { return -ENOTSUP; }
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static int reg_165_port_toggle_bits(const struct device *dev, uint32_t mask) { return -ENOTSUP; }
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static const struct gpio_driver_api api_table = {
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.pin_configure = reg_165_pin_config,
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.port_get_raw = reg_165_port_get_raw,
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.port_set_masked_raw = reg_165_port_set_masked_raw,
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.port_set_bits_raw = reg_165_port_set_bits_raw,
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.port_clear_bits_raw = reg_165_port_clear_bits_raw,
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.port_toggle_bits = reg_165_port_toggle_bits,
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};
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/**
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* @brief Initialization function of 165
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*
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* @param dev Device struct
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* @return 0 if successful, failed otherwise.
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*/
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static int reg_165_init(const struct device *dev) {
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const struct reg_165_config *const config = dev->config;
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struct reg_165_drv_data *const drv_data = (struct reg_165_drv_data *const)dev->data;
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if (!device_is_ready(config->bus.bus)) {
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LOG_ERR("Unable to get SPI bus device");
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return -ENODEV;
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}
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for (int i = 0; i < config->load_gpios_len; i++) {
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int err = gpio_pin_configure_dt(&config->load_gpios[i], GPIO_OUTPUT);
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if (err) {
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LOG_ERR("Unable to configure pin %u on %s for output", config->load_gpios[i].pin,
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config->load_gpios[i].port->name);
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return err;
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}
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err = gpio_pin_set_dt(&config->load_gpios[i], 1);
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if (err) {
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LOG_ERR("Unable to set pin %u on %s to idle value '1'", config->load_gpios[i].pin,
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config->load_gpios[i].port->name);
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return err;
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}
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}
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k_sem_init(&drv_data->lock, 1, 1);
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return 0;
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}
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#define GPIO_PORT_PIN_MASK_FROM_NGPIOS(ngpios) ((gpio_port_pins_t)(((uint64_t)1 << (ngpios)) - 1U))
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#define GPIO_PORT_PIN_MASK_FROM_DT_INST(inst) \
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GPIO_PORT_PIN_MASK_FROM_NGPIOS(DT_INST_PROP(inst, ngpios))
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#define REG_165_INIT(n) \
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static const struct gpio_dt_spec load_gpios_##n[] = { \
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COND_CODE_1(DT_INST_NODE_HAS_PROP(n, load_gpios), \
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(LISTIFY(LOAD_GPIOS_LEN(n), LOAD_GPIO_CFG_INIT, (, ), n)), ())}; \
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static struct reg_165_config reg_165_##n##_config = { \
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.common = \
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{ \
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n), \
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}, \
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.bus = \
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SPI_DT_SPEC_INST_GET(n, SPI_OP_MODE_MASTER | SPI_TRANSFER_MSB | SPI_WORD_SET(8), 0), \
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.ngpios = DT_INST_PROP(n, ngpios), \
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.load_gpios = load_gpios_##n, \
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.load_gpios_len = ARRAY_SIZE(load_gpios_##n), \
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}; \
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\
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static struct reg_165_drv_data reg_165_##n##_drvdata = {}; \
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\
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/* This has to init after SPI master */ \
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DEVICE_DT_INST_DEFINE(n, reg_165_init, NULL, ®_165_##n##_drvdata, ®_165_##n##_config, \
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POST_KERNEL, CONFIG_GPIO_165_INIT_PRIORITY, &api_table);
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DT_INST_FOREACH_STATUS_OKAY(REG_165_INIT)
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34
app/drivers/zephyr/dts/bindings/gpio/zmk,gpio-165.yaml
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34
app/drivers/zephyr/dts/bindings/gpio/zmk,gpio-165.yaml
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@ -0,0 +1,34 @@
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#
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# Copyright (c) 2022 The ZMK Contributors
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#
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# SPDX-License-Identifier: MIT
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#
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description: >
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This is a representation of the 165 Parrallel-in Shift Register.
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compatible: "zmk,gpio-165"
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include: [gpio-controller.yaml, spi-device.yaml]
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properties:
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"#gpio-cells":
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const: 2
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ngpios:
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type: int
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required: true
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enum:
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- 8
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- 16
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- 24
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- 32
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description: Number of gpios supported
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load-gpios:
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type: phandle-array
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description: GPIO to which the /PL a.k.a. SH/LD pin is connected
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gpio-cells:
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- pin
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- flags
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