2403ecb046
This is an input-only gpio driver for use with 74x165 style parallel-input shift registers, (using SPI peripheral) The user can choose to either use cs-gpios of spi or load-gpios for connecting to the SH/LD pin of the shift register. The difference is that cs-gpios will keep the input latch enabled while idle, and load-gpios will instead pulse the SH/LD signal before the register content is shifted. In both cases the gpio should be configured GPIO_ACTIVE_HIGH.
34 lines
562 B
YAML
34 lines
562 B
YAML
#
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# Copyright (c) 2022 The ZMK Contributors
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#
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# SPDX-License-Identifier: MIT
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#
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description: >
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This is a representation of the 165 Parrallel-in Shift Register.
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compatible: "zmk,gpio-165"
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include: [gpio-controller.yaml, spi-device.yaml]
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properties:
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"#gpio-cells":
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const: 2
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ngpios:
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type: int
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required: true
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enum:
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- 8
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- 16
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- 24
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- 32
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description: Number of gpios supported
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load-gpios:
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type: phandle-array
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description: GPIO to which the /PL a.k.a. SH/LD pin is connected
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gpio-cells:
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- pin
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- flags
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