kb01/zmk
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

feat(boards): Add Choconum board.

Browse source
This commit is contained in:
Peter Johanson 2021-09-15 15:26:58 -04:00
parent 33fa15a235
commit 073ae70fa3
14 changed files with 331 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

8
app/boards/arm/choconum/Kconfig.board Normal file
View file

@ -0,0 +1,8 @@
# keeb.io Choconum board configuration
# Copyright (c) 2020 The ZMK Contributors
# SPDX-License-Identifier: MIT
config BOARD_CHOCONUM
bool "Choconum"
depends on SOC_STM32F072XB

17
app/boards/arm/choconum/Kconfig.defconfig Normal file
View file

@ -0,0 +1,17 @@
# keeb.io Choconum board configuration
# Copyright (c) 2020 Pete Johanson
# SPDX-License-Identifier: MIT
if BOARD_CHOCONUM
config BOARD
default "choconum"
config ZMK_KEYBOARD_NAME
default "Choconum"
config ZMK_USB
default y
endif # BOARD_CHOCONUM

16
app/boards/arm/choconum/README.md Normal file
View file

@ -0,0 +1,16 @@
# Building ZMK for the Choconum
Some general notes/commands for building standard Choconum layouts from the assembly documentation.
## Standard Build
```
west build -p -d build/choconum --board choconum
```
## Flashing
```
west flash -d build/choconum
```

7
app/boards/arm/choconum/board.cmake Normal file
View file

@ -0,0 +1,7 @@
# SPDX-License-Identifier: MIT
board_runner_args(dfu-util "--pid=0483:df11" "--alt=0" "--dfuse")
board_runner_args(jlink "--device=STM32F072CB" "--speed=4000")
include(${ZEPHYR_BASE}/boards/common/dfu-util.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)

43
app/boards/arm/choconum/choconum.dts Normal file
View file

@ -0,0 +1,43 @@
/*
* Copyright (c) 2021 The ZMK Contributors
*
* SPDX-License-Identifier: MIT
*/
#include "choconum_base.dtsi"
/ {
chosen {
zmk,kscan = &kscan;
};
kscan: kscan {
compatible = "zmk,kscan-gpio-direct";
label = "KSCAN";
input-gpios
= <&gpiob 2 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>
, <&gpiob 10 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>
, <&gpiob 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>
, <&gpiob 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>
, <&gpiob 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>
, <&gpiob 11 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>
, <&gpioa 15 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>
, <&gpiob 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>
, <&gpiob 0 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>
, <&gpioa 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>
, <&gpiob 7 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>
, <&gpioa 7 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>
, <&gpioa 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>
, <&gpiob 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>
, <&gpiob 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>
, <&gpioa 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>
, <&gpiob 9 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>
;
};
};

26
app/boards/arm/choconum/choconum.keymap Normal file
View file

@ -0,0 +1,26 @@
/*
* Copyright (c) 2020 The ZMK Contributors
*
* SPDX-License-Identifier: MIT
*/
#include <behaviors.dtsi>
#include <dt-bindings/zmk/keys.h>
/ {
keymap {
compatible = "zmk,keymap";
default_layer {
bindings = <
&kp KP_NUMLOCK &kp KP_DIVIDE &kp KP_MULTIPLY &kp KP_MINUS
&kp KP_N7 &kp KP_N8 &kp KP_N9 &kp KP_PLUS
&kp KP_N4 &kp KP_N5 &kp KP_N6
&kp KP_N1 &kp KP_N2 &kp KP_N3 &kp KP_ENTER
&kp KP_N0 &kp KP_DOT
>;
};
};
};

14
app/boards/arm/choconum/choconum.yaml Normal file
View file

@ -0,0 +1,14 @@
identifier: choconum
name: keeb.io Choconum
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 40
supported:
- encoders
- switches
- underglow
- per_key

10
app/boards/arm/choconum/choconum.zmk.yml Normal file
View file

@ -0,0 +1,10 @@
file_format: "1"
id: choconum
name: Choconum
type: board
arch: arm
features:
- keys
outputs:
- usb
url: https://keeb.io/products/choconum-kailh-choc-numpad

44
app/boards/arm/choconum/choconum_base.dtsi Normal file
View file

@ -0,0 +1,44 @@
/*
* Copyright (c) 2020 The ZMK Contributors
*
* SPDX-License-Identifier: MIT
*/
/dts-v1/;
#include <st/f0/stm32f072Xb.dtsi>
/ {
model = "Keeb.io Choconum";
compatible = "keebio,choconum", "st,stm32f072";
chosen {
zephyr,sram = &sram0;
zephyr,flash = &flash0;
};
};
&usb {
status = "okay";
};
&rtc {
status = "okay";
};
&flash0 {
/*
* For more information, see:
* http://docs.zephyrproject.org/latest/guides/dts/index.html#flash-partitions
*/
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
/* Set 6Kb of storage at the end of the 128Kb of flash */
storage_partition: partition@3e800 {
label = "storage";
reg = <0x0001e800 0x00001800>;
};
};
};

32
app/boards/arm/choconum/choconum_defconfig Normal file
View file

@ -0,0 +1,32 @@
# SPDX-License-Identifier: MIT
CONFIG_SOC_SERIES_STM32F0X=y
CONFIG_SOC_STM32F072XB=y
# 72MHz system clock
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=72000000
# Floating Point Options
CONFIG_FPU=y
# enable GPIO
CONFIG_GPIO=y
# enable pinmux
CONFIG_PINMUX=y
# Needed to reduce this to size that will fit on F072
CONFIG_HEAP_MEM_POOL_SIZE=1024
# clock configuration
CONFIG_CLOCK_CONTROL=y
# Clock configuration for Cube Clock control driver
CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
# use HSI as PLL input
CONFIG_CLOCK_STM32_PLL_SRC_HSI=y
# produce 72MHz clock at PLL output
CONFIG_CLOCK_STM32_PLL_PREDIV=1
CONFIG_CLOCK_STM32_PLL_MULTIPLIER=12
CONFIG_CLOCK_STM32_AHB_PRESCALER=1
CONFIG_CLOCK_STM32_APB1_PRESCALER=2
CONFIG_CLOCK_STM32_APB2_PRESCALER=1

46
app/boards/arm/choconum/choconum_ortho.dts Normal file
View file

@ -0,0 +1,46 @@
/*
* Copyright (c) 2021 The ZMK Contributors
*
* SPDX-License-Identifier: MIT
*/
#include "choconum_base.dtsi"
/ {
chosen {
zmk,kscan = &kscan;
};
kscan: kscan {
compatible = "zmk,kscan-gpio-direct";
label = "KSCAN";
input-gpios
= <&gpiob 2 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>
, <&gpiob 10 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>
, <&gpiob 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>
, <&gpiob 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>
, <&gpiob 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>
, <&gpiob 11 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>
, <&gpioa 15 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>
, <&gpiob 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>
, <&gpiob 0 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>
, <&gpioa 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>
, <&gpiob 7 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>
, <&gpiof 0 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>
, <&gpioa 7 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>
, <&gpioa 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>
, <&gpiob 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>
, <&gpiob 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>
, <&gpioa 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>
, <&gpioa 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>
, <&gpiob 9 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>
, <&gpiof 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>
;
};
};

26
app/boards/arm/choconum/choconum_ortho.keymap Normal file
View file

@ -0,0 +1,26 @@
/*
* Copyright (c) 2020 The ZMK Contributors
*
* SPDX-License-Identifier: MIT
*/
#include <behaviors.dtsi>
#include <dt-bindings/zmk/keys.h>
/ {
keymap {
compatible = "zmk,keymap";
default_layer {
bindings = <
&kp KP_NUMLOCK &kp KP_DIVIDE &kp KP_MULTIPLY &kp KP_MINUS
&kp KP_N7 &kp KP_N8 &kp KP_N9 &kp KP_PLUS
&kp KP_N4 &kp KP_N5 &kp KP_N6 &kp KP_PLUS
&kp KP_N1 &kp KP_N2 &kp KP_N3 &kp KP_ENTER
&kp KP_N0 &kp KP_N0 &kp KP_DOT &kp KP_ENTER
>;
};
};
};

10
app/boards/arm/choconum/choconum_ortho.zmk.yml Normal file
View file

@ -0,0 +1,10 @@
file_format: "1"
id: choconum_ortho
name: Choconum (Ortho Layout)
type: board
arch: arm
features:
- keys
outputs:
- usb
url: https://keeb.io/products/choconum-kailh-choc-numpad

32
app/boards/arm/choconum/choconum_ortho_defconfig Normal file
View file

@ -0,0 +1,32 @@
# SPDX-License-Identifier: MIT
CONFIG_SOC_SERIES_STM32F0X=y
CONFIG_SOC_STM32F072XB=y
# 72MHz system clock
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=72000000
# Floating Point Options
CONFIG_FPU=y
# enable GPIO
CONFIG_GPIO=y
# enable pinmux
CONFIG_PINMUX=y
# Needed to reduce this to size that will fit on F072
CONFIG_HEAP_MEM_POOL_SIZE=1024
# clock configuration
CONFIG_CLOCK_CONTROL=y
# Clock configuration for Cube Clock control driver
CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
# use HSI as PLL input
CONFIG_CLOCK_STM32_PLL_SRC_HSI=y
# produce 72MHz clock at PLL output
CONFIG_CLOCK_STM32_PLL_PREDIV=1
CONFIG_CLOCK_STM32_PLL_MULTIPLIER=12
CONFIG_CLOCK_STM32_AHB_PRESCALER=1
CONFIG_CLOCK_STM32_APB1_PRESCALER=2
CONFIG_CLOCK_STM32_APB2_PRESCALER=1