Initial commit of Preonic rev3 board definition. Awaiting ticket #202 before it can be tested.
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9
app/boards/arm/preonic/CMakeLists.txt
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9
app/boards/arm/preonic/CMakeLists.txt
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# SPDX-License-Identifier: MIT
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list(APPEND EXTRA_DTC_FLAGS "-qq")
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if(CONFIG_PINMUX)
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zephyr_library()
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zephyr_library_sources(pinmux.c)
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zephyr_library_include_directories(${ZEPHYR_BASE}/drivers)
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endif()
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8
app/boards/arm/preonic/Kconfig.board
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8
app/boards/arm/preonic/Kconfig.board
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# Preonic V3 board configuration
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# Copyright (c) 2020 The ZMK Contributors
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# SPDX-License-Identifier: MIT
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config BOARD_PREONIC_REV3
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bool "Preonic V3 Keyboard"
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depends on SOC_STM32F303XC
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14
app/boards/arm/preonic/Kconfig.defconfig
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14
app/boards/arm/preonic/Kconfig.defconfig
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# Preonic keyboard configuration
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# Copyright (c) 2020 The ZMK Contributors
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# SPDX-License-Identifier: MIT
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if BOARD_PREONIC_REV3
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config ZMK_KEYBOARD_NAME
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default "Preonic V3"
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config ZMK_USB
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default y
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endif # BOARD_PREONIC_REV3
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7
app/boards/arm/preonic/board.cmake
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7
app/boards/arm/preonic/board.cmake
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# SPDX-License-Identifier: MIT
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board_runner_args(dfu-util "--pid=0483:df11" "--alt=0" "--dfuse")
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board_runner_args(jlink "--device=STM32F303VC" "--speed=4000")
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include(${ZEPHYR_BASE}/boards/common/dfu-util.board.cmake)
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include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
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67
app/boards/arm/preonic/pinmux.c
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67
app/boards/arm/preonic/pinmux.c
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/*
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* Copyright (c) 2017 I-SENSE group of ICCS
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*
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* SPDX-License-Identifier: MIT
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*/
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#include <kernel.h>
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#include <device.h>
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#include <init.h>
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#include <drivers/pinmux.h>
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#include <sys/sys_io.h>
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#include <pinmux/stm32/pinmux_stm32.h>
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/* pin assignments for STM32F3DISCOVERY board */
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static const struct pin_config pinconf[] = {
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#ifdef CONFIG_UART_1
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{STM32_PIN_PC4, STM32F3_PINMUX_FUNC_PC4_USART1_TX},
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{STM32_PIN_PC5, STM32F3_PINMUX_FUNC_PC5_USART1_RX},
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#endif /* CONFIG_UART_1 */
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#ifdef CONFIG_UART_2
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{STM32_PIN_PA2, STM32F3_PINMUX_FUNC_PA2_USART2_TX},
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{STM32_PIN_PA3, STM32F3_PINMUX_FUNC_PA3_USART2_RX},
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#endif /* CONFIG_UART_2 */
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#ifdef CONFIG_I2C_1
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{STM32_PIN_PB6, STM32F3_PINMUX_FUNC_PB6_I2C1_SCL},
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{STM32_PIN_PB7, STM32F3_PINMUX_FUNC_PB7_I2C1_SDA},
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#endif /* CONFIG_I2C_1 */
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#ifdef CONFIG_I2C_2
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{STM32_PIN_PA9, STM32F3_PINMUX_FUNC_PA9_I2C2_SCL},
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{STM32_PIN_PA10, STM32F3_PINMUX_FUNC_PA10_I2C2_SDA},
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#endif /* CONFIG_I2C_2 */
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#ifdef CONFIG_SPI_1
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#ifdef CONFIG_SPI_STM32_USE_HW_SS
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{STM32_PIN_PA4, STM32F3_PINMUX_FUNC_PA4_SPI1_NSS},
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#endif /* CONFIG_SPI_STM32_USE_HW_SS */
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{STM32_PIN_PA5, STM32F3_PINMUX_FUNC_PA5_SPI1_SCK},
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{STM32_PIN_PA6, STM32F3_PINMUX_FUNC_PA6_SPI1_MISO},
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{STM32_PIN_PA7, STM32F3_PINMUX_FUNC_PA7_SPI1_MOSI},
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#endif /* CONFIG_SPI_1 */
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#ifdef CONFIG_SPI_2
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#ifdef CONFIG_SPI_STM32_USE_HW_SS
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{STM32_PIN_PB12, STM32F3_PINMUX_FUNC_PB12_SPI2_NSS},
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#endif /* CONFIG_SPI_STM32_USE_HW_SS */
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{STM32_PIN_PB13, STM32F3_PINMUX_FUNC_PB13_SPI2_SCK},
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{STM32_PIN_PB14, STM32F3_PINMUX_FUNC_PB14_SPI2_MISO},
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{STM32_PIN_PB15, STM32F3_PINMUX_FUNC_PB15_SPI2_MOSI},
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#endif /* CONFIG_SPI_2 */
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#ifdef CONFIG_USB_DC_STM32
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{STM32_PIN_PA11, STM32F3_PINMUX_FUNC_PA11_USB_DM},
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{STM32_PIN_PA12, STM32F3_PINMUX_FUNC_PA12_USB_DP},
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#endif /* CONFIG_USB_DC_STM32 */
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#ifdef CONFIG_CAN_1
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{STM32_PIN_PD0, STM32F3_PINMUX_FUNC_PD0_CAN1_RX},
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{STM32_PIN_PD1, STM32F3_PINMUX_FUNC_PD1_CAN1_TX},
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#endif /* CONFIG_CAN_1 */
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};
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static int pinmux_stm32_init(struct device *port) {
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ARG_UNUSED(port);
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stm32_setup_pins(pinconf, ARRAY_SIZE(pinconf));
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return 0;
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}
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SYS_INIT(pinmux_stm32_init, PRE_KERNEL_1, CONFIG_PINMUX_STM32_DEVICE_INITIALIZATION_PRIORITY);
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96
app/boards/arm/preonic/preonic_rev3.dts
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app/boards/arm/preonic/preonic_rev3.dts
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/*
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* Copyright (c) 2017 I-SENSE group of ICCS
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*
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* SPDX-License-Identifier: MIT
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*/
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/dts-v1/;
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#include <st/f3/stm32f303Xc.dtsi>
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#include <dt-bindings/zmk/matrix-transform.h>
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/ {
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model = "Preonic PCD, rev3";
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compatible = "preonic,rev3", "st,stm32f303";
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chosen {
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zephyr,sram = &sram0;
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zephyr,flash = &flash0;
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zmk,kscan = &kscan0;
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zmk,matrix_transform = &my_transform;
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};
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default_transform: keymap_transform_0 {
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compatible = "zmk,matrix-transform";
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columns = <6>;
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rows = <10>;
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map = <
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RC(0,0) RC(0,1) RC(0,2) RC(0,3) RC(0,4) RC(0,5) RC(4,0) RC(4,1) RC(4,2) RC(4,3) RC(4,4) RC(4,5)
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RC(1,0) RC(1,1) RC(1,2) RC(1,3) RC(1,4) RC(1,5) RC(5,0) RC(5,1) RC(5,2) RC(5,3) RC(5,4) RC(5,5)
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RC(2,0) RC(2,1) RC(2,2) RC(2,3) RC(2,4) RC(2,5) RC(6,0) RC(6,1) RC(6,2) RC(6,3) RC(6,4) RC(6,5)
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RC(3,0) RC(3,1) RC(3,2) RC(3,3) RC(3,4) RC(3,5) RC(7,0) RC(7,1) RC(7,2) RC(7,3) RC(7,4) RC(7,5)
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RC(8,0) RC(8,1) RC(8,2) RC(9,3) RC(9,4) RC(9,5) RC(9,0) RC(9,1) RC(9,2) RC(8,3) RC(8,4) RC(8,5)
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>;
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};
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my_transform: keymap_transform_0 {
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compatible = "zmk,matrix-transform";
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columns = <6>;
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rows = <10>;
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map = <
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RC(0,0) RC(0,1) RC(0,2) RC(0,3) RC(0,4) RC(0,5) RC(7,0) RC(7,1) RC(7,2) RC(7,3) RC(7,4) RC(7,5)
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RC(2,0) RC(2,1) RC(2,2) RC(2,3) RC(2,4) RC(2,5) RC(3,0) RC(3,1) RC(3,2) RC(3,3) RC(3,4) RC(3,5)
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RC(4,0) RC(4,1) RC(4,2) RC(4,3) RC(4,4) RC(4,5) RC(5,0) RC(5,1) RC(5,2) RC(5,3) RC(5,4) RC(5,5)
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RC(6,0) RC(6,1) RC(6,2) RC(6,3) RC(6,4) RC(6,5) RC(1,0) RC(1,1) RC(1,2) RC(1,3) RC(1,4) RC(1,5)
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RC(8,0) RC(8,1) RC(8,2) RC(9,3) RC(9,4) RC(9,5) RC(9,0) RC(9,1) RC(9,2) RC(8,3) RC(8,4) RC(8,5)
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>;
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};
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kscan0: kscan_0 {
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compatible = "zmk,kscan-gpio-matrix";
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label = "KSCAN";
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diode-direction = "col2row";
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row-gpios
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= <&gpioa 10 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>
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, <&gpiob 15 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>
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, <&gpioa 9 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>
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, <&gpioa 2 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>
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, <&gpioa 8 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>
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, <&gpioa 6 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>
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, <&gpioc 13 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>
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, <&gpioc 14 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>
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, <&gpioc 15 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>
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, <&gpioa 3 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>
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;
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col-gpios
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= <&gpiob 11 GPIO_ACTIVE_HIGH>
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, <&gpiob 10 GPIO_ACTIVE_HIGH>
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, <&gpiob 2 GPIO_ACTIVE_HIGH>
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, <&gpiob 1 GPIO_ACTIVE_HIGH>
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, <&gpioa 7 GPIO_ACTIVE_HIGH>
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, <&gpiob 0 GPIO_ACTIVE_HIGH>
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;
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};
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};
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&usb {
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status = "okay";
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};
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&flash0 {
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/*
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* For more information, see:
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* http://docs.zephyrproject.org/latest/guides/dts/index.html#flash-partitions
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*/
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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/* Set 6Kb of storage at the end of the 256Kb of flash */
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storage_partition: partition@3e800 {
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label = "storage";
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reg = <0x0003e800 0x00001800>;
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};
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};
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};
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23
app/boards/arm/preonic/preonic_rev3.keymap
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app/boards/arm/preonic/preonic_rev3.keymap
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#include <behaviors.dtsi>
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#include <dt-bindings/zmk/keys.h>
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/ {
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keymap {
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compatible = "zmk,keymap";
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default_layer {
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// -----------------------------------------------------------------------------------------
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// | TAB | Q | W | E | R | T | Y | U | I | O | P | BSPC |
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// | ESC | A | S | D | F | G | H | J | K | L | ; | ' |
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// | SHIFT | Z | X | C | V | B | N | M | , | . | / | RET |
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// | FN | LGUI | LALT | LCTL | LOWR | SPACE | RAIS | LARW | DARW | UARW | RARW |
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bindings = <
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&kp TAB &kp NUM_1 &kp NUM_2 &kp NUM_3 &kp NUM_4 &kp NUM_5 &kp NUM_6 &kp NUM_7 &kp NUM_8 &kp NUM_9 &kp NUM_0 &kp DEL
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&kp TAB &kp Q &kp W &kp E &kp R &kp T &kp Y &kp U &kp I &kp O &kp P &kp DEL
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&kp ESC &kp A &kp S &kp D &kp F &kp G &kp H &kp J &kp K &kp L &kp SCLN &kp QUOT
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&kp LSFT &kp Z &kp X &kp C &kp V &kp B &kp N &kp M &kp CMMA &kp DOT &kp BSLH &kp RET
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&trans &kp LGUI &kp LALT &kp LCTL &trans &trans &kp SPC &trans &kp LARW &kp DARW &kp UARW &kp RARW
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>;
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};
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};
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};
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19
app/boards/arm/preonic/preonic_rev3.yaml
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app/boards/arm/preonic/preonic_rev3.yaml
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identifier: preonic_rev3
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name: PREONICREV3
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type: keyboard
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arch: arm
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toolchain:
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- zephyr
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- gnuarmemb
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- xtools
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ram: 40
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supported:
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- gpio
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- i2c
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- counter
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- spi
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- usb_device
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- lsm303dlhc
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- nvs
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- can
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- kscan
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28
app/boards/arm/preonic/preonic_rev3_defconfig
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28
app/boards/arm/preonic/preonic_rev3_defconfig
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# SPDX-License-Identifier: MIT
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CONFIG_SOC_SERIES_STM32F3X=y
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CONFIG_SOC_STM32F303XC=y
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# 72MHz system clock
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CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=72000000
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# enable pinmux
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CONFIG_PINMUX=y
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# enable GPIO
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CONFIG_GPIO=y
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# clock configuration
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CONFIG_CLOCK_CONTROL=y
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# Clock configuration for Cube Clock control driver
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CONFIG_CLOCK_STM32_HSE_CLOCK=8000000
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CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
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# use HSE as PLL input
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CONFIG_CLOCK_STM32_PLL_SRC_HSE=y
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# produce 72MHz clock at PLL output
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CONFIG_CLOCK_STM32_PLL_PREDIV=1
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CONFIG_CLOCK_STM32_PLL_MULTIPLIER=9
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CONFIG_CLOCK_STM32_AHB_PRESCALER=1
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CONFIG_CLOCK_STM32_APB1_PRESCALER=2
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CONFIG_CLOCK_STM32_APB2_PRESCALER=1
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